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2.5 v to 5.5 v, 500 a, 2-wire interface quad voltage output, 8-/10-/12-bit dacs ad5305/ad5315/ad5325 rev. g information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features ad5305: 4 buffered 8-bit dacs in 10-lead msop a version: 1 lsb inl, b version: 0.625 lsb inl ad5315: 4 buffered 10-bit dacs in 10-lead msop a version: 4 lsb inl, b version: 2.5 lsb inl ad5325: 4 buffered 12-bit dacs in 10-lead msop a version: 16 lsb inl, b version: 10 lsb inl low power operation: 500 a @ 3 v, 600 a @ 5 v 2-wire (i 2 c?-compatible) serial interface 2.5 v to 5.5 v power supply guaranteed monotonic by design over all codes power-down to 80 na @ 3 v, 200 na @ 5 v three power-down modes double-buffered input logic output range: 0 v to v ref power-on reset to 0 v simultaneous update of outputs ( ldac function) software clear facility data readback facility on-chip rail-to-rail output buffer amplifiers temperature range: ?40c to +105c applications portable battery-powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators industrial process control general description the ad5305/ad5315/ad5325 1 are quad 8-, 10-, and 12-bit buffered voltage output dacs in a 10-lead msop that operate from a single 2.5 v to 5.5 v supply, consuming 500 a at 3 v. their on-chip output amplifiers allow rail-to-rail output swing with a slew rate of 0.7 v/s. a 2-wire serial interface that operates at clock rates up to 400 khz is used. this interface is smbus compatible at v dd < 3.6 v. multiple devices can be placed on the same bus. the references for the four dacs are derived from one reference pin. the outputs of all dacs can be updated simultaneously using the software ldac function. the parts incorporate a power-on reset circuit, which ensures that the dac outputs power up to 0 v and remain there until a valid write takes place to the device. there is also a software clear function to reset all input and dac registers to 0 v. the parts contain a power-down feature that reduces the current consumption of the devices to 200 na @ 5 v (80 na @ 3 v). the low power consumption of these parts in normal operation makes them ideally suited for portable battery-operated equip- ment. the power consumption is 3 mw at 5 v, 1.5 mw at 3 v, reducing to 1 w in power-down mode. 1 protected by u.s. patent no. 5,969,657 and 5,684,481. functional block diagram ref in gnd ad5305/ad5315/ad5325 s d a scl a0 buffer buffer buffer buffer input register input register input register input register v dd ldac power-on reset interface logic power-down logic string dac a string dac b string dac c string dac d dac register dac register dac register dac register 00930-001 v out d v out c v out b v out a figure 1.
ad5305/ad5315/ad5325 rev. g | page 2 of 24 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 ac characteristics........................................................................ 5 timing characteristics ................................................................ 5 absolute maximum ratings............................................................ 7 esd caution.................................................................................. 7 pin configuration and function descriptions............................. 8 typical performance characteristics ............................................. 9 terminology .................................................................................... 13 functional description .................................................................. 15 digital-to-analog section ......................................................... 15 resistor string ............................................................................. 15 dac reference inputs ............................................................... 15 output amplifier........................................................................ 15 power-on reset .......................................................................... 15 serial interface ............................................................................ 16 read/write sequence................................................................. 16 pointer byte bits ......................................................................... 16 input shift register .................................................................... 16 default readback condition .................................................... 17 multiple-dac write sequence................................................. 17 multiple-dac readback sequence ......................................... 17 write operation.......................................................................... 17 read operation........................................................................... 17 double-buffered interface ........................................................ 18 power-down modes .................................................................. 18 applications..................................................................................... 20 typical application circuit....................................................... 20 bipolar operation....................................................................... 20 multiple devices on one bus ................................................... 20 ad5305/ad5315/ad5325 as a digitally programmable window detector ....................................................................... 21 coarse and fine adjustment using the ad5305/ad5315/ad5325 ....................................................... 21 power supply decoupling ......................................................... 21 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 23 revision history 5/06rev. f to rev. g updated format..................................................................universal changes to ordering guide .......................................................... 24 10/04rev. e to rev. f changes to figure 6........................................................................ 11 changes to pointer byte bits section ........................................... 12 changes to figure 7........................................................................ 12 8/03rev. d to rev. e added a version.................................................................universal changes to features.......................................................................... 1 changes to specifications ................................................................ 2 changes to absolute maximum ratings ....................................... 5 changes to ordering guide ............................................................ 5 changes to tpc 21......................................................................... 10 added octals section to table ii.................................................. 18 updated outline dimensions....................................................... 19 4/01rev. c to rev. d edit to features section ....................................................................1 edit to figure 6 ..................................................................................1 edits to right/left and double sections of pointer byte bits section........................................................... 11 edit to input shift register section.............................................. 12 edit to multiple-dac readback sequence section................... 12 edits to figure 7.............................................................................. 12 edits to write operation section.................................................. 13 edits to figure 8.............................................................................. 13 edits to read operation section................................................... 14 edits to figure 9.............................................................................. 14 edits to power-down modes section .......................................... 15 edits to figure 12............................................................................ 16
ad5305/ad5315/ad5325 rev. g | page 3 of 24 specifications v dd = 2.5 v to 5.5 v, v ref = 2 v, r l = 2 k to gnd, c l = 200 pf to gnd, all specifications t min to t max , unless otherwise noted. table 1. a version 1 b version 1 parameter 2 min typ max min typ max unit conditions/comments dc performance 3 , 4 ad5305 resolution 8 8 bits relative accuracy 0.15 1 0.15 0.625 lsb differential nonlinearity 0.02 0.25 0.02 0.25 lsb guaranteed monotonic by design over all codes ad5315 resolution 10 10 bits relative accuracy 0.5 4 0.5 2.5 lsb differential nonlinearity 0.05 0.5 0.05 0.5 lsb guaranteed monotonic by design over all codes ad5325 resolution 12 12 bits relative accuracy 2 16 2 10 lsb differential nonlinearity 0.2 1 0.2 1 lsb guaranteed monotonic by design over all codes offset error 0.4 3 0.4 3 % of fsr gain error 0.15 1 0.15 1 % of fsr lower deadband 20 60 20 60 mv lower deadband exists only if offset error is negative offset error drift 5 ?12 ?12 ppm of fsr/c gain error drift 5 ?5 ?5 ppm of fsr/c power supply rejection ratio 5 C60 C60 db ?v dd = 10% dc crosstalk 5 200 200 v r l = 2 k to gnd or v dd dac reference inputs 5 v ref input range 0.25 v dd 0.25 v dd v v ref input impedance 37 45 37 45 k normal operation >10 >10 m power-down mode reference feedthrough ?90 ?90 db frequency = 10 khz output characteristics 5 minimum output voltage 6 0.001 0.001 v a measure of the minimum and maximum drive capability of the output amplifier maximum output voltage 6 v dd ? 0.001 v dd ? 0.001 v dc output impedance 0.5 0.5 short-circuit current 25 25 ma v dd = 5 v 16 16 ma v dd = 3 v power-up time 2.5 2.5 s coming out of power-down mode v dd = 5 v 5 5 s coming out of power-down mode v dd = 3 v
ad5305/ad5315/ad5325 rev. g | page 4 of 24 a version 1 b version 1 parameter 2 min typ max min typ max unit conditions/comments logic inputs (a0 ) 5 input current 1 1 a input low voltage, v il 0.8 0.8 v v dd = 5 v 10% 0.6 0.6 v v dd = 3 v 10% 0.5 0.5 v v dd = 2.5 v input high voltage, v ih 2.4 2.4 v v dd = 5 v 10% 2.1 2.1 v v dd = 3 v 10% 2.0 2.0 v v dd = 2.5 v pin capacitance 3 3 pf logic inputs (scl, sda) 5 input high voltage, v ih 0.7 v dd v dd + 0.3 0.7 v dd v dd + 0.3 v smbus compatible at v dd < 3.6 v input low voltage, v il ?0.3 0.3 v dd ?0.3 0.3 v dd v smbus compatible at v dd < 3.6 v input leakage current, i in 1 1 a input hysteresis, v hyst 0.05 v dd 0.05 v dd v input capacitance, c in 8 8 pf glitch rejection 50 50 ns input filtering suppresses noise spikes of less than 50 ns logic output (sda) 5 output low voltage, v ol 0.4 0.4 v i sink = 3 ma 0.6 0.6 v i sink = 6 ma three-state leakage current 1 1 a three-state output capacitance 8 8 pf power requirements v dd 2.5 5.5 2.5 5.5 v i dd (normal mode) 7 v ih = v dd and v il = gnd v dd = 4.5 v to 5.5 v 600 900 600 900 a v dd = 2.5 v to 3.6 v 500 700 500 700 a i dd (power-down mode) v ih = v dd and v il = gnd v dd = 4.5 v to 5.5 v 0.2 1 0.2 1 a i dd = 4 a (maximum) during 0 readback on sda v dd = 2.5 v to 3.6 v 0.08 1 0.08 1 a i dd = 1.5 a (maximum) during 0 readback on sda 1 temperature range (a, b version): ? 40c to +105c; ty pical at +25c. 2 see the terminology section. 3 dc specifications tested with the outputs unloaded. 4 linearity is tested using a reduce d code range: ad5305 (code 8 to 248); ad 5315 (code 28 to 995); ad 5325 (code 115 to 3981). 5 guaranteed by design and characterization, not production tested. 6 for the amplifier output to reach its minimum voltage, offset e rror must be negative; to reach its maximum voltage, v ref = v dd and offset plus gain error must be positive. 7 i dd specification is valid fo r all dac codes. interface inactive. all dacs active and excluding load currents.
ad5305/ad5315/ad5325 rev. g | page 5 of 24 ac characteristics v dd = 2.5 v to 5.5 v, r l = 2 k to gnd, c l = 200 pf to gnd, all specifications t min to t max , unless otherwise noted. table 2. a, b version 1 parameter 2 , 3 min typ max unit conditions/comments output voltage settling time v ref = v dd = 5 v ad5305 6 8 s ? scale to ? scale change (040 to 0c0) ad5315 7 9 s ? scale to ? scale change (0100 to 0300) ad5325 8 10 s ? scale to ? scale change (0400 to 0c00) slew rate 0.7 v/s major-code transition glitch energy 12 nv-s 1 lsb change around major carry digital feedthrough 1 nv-s digital crosstalk 1 nv-s dac-to-dac crosstalk 3 nv-s multiplying bandwidth 200 khz v ref = 2 v 0.1 v p-p total harmonic distortion ?70 db v ref = 2.5 v 0.1 v p-p, frequency = 10 khz 1 temperature range (a, b version): ? 40c to +105c; ty pical at +25c. 2 guaranteed by design and characterization, not production tested. 3 see the terminology section. timing characteristics v dd = 2.5 v to 5.5 v, all specifications t min to t max , unless otherwise noted. table 3. parameter 1 , 2 limit at t min , t max (a, b version) unit conditions/comments f scl 400 khz max scl clock frequency t 1 2.5 s min scl cycle time t 2 0.6 s min t high , scl high time t 3 1.3 s min t low , scl low time t 4 0.6 s min t hd,sta , start/repeated start condition hold time t 5 100 ns min t su,dat , data setup time t 6 3 0.9 s max t hd,dat , data hold time 0 s min t hd,dat , data hold time t 7 0.6 s min t su,sta , setup time for repeated start t 8 0.6 s min t su,sto , stop condition setup time t 9 1.3 s min t buf , bus-free time between a stop and a start condition t 10 300 ns max t r , rise time of scl and sda when receiving 0 ns min t r , rise time of scl and sda when receiving (cmos compatible) t 11 250 ns max t f , fall time of sda when transmitting 0 ns min t f , fall time of sda when receiving (cmos compatible) 300 ns max t f , fall time of scl and sda when receiving 20 + 0.1 c b 4 ns min t f , fall time of scl and sda when transmitting c b 4 400 pf max capacitive load for each bus line 1 see figure 2. 2 guaranteed by design and characterization; not production tested. 3 a master device must provide a hold time of at least 300 ns fo r the sda signal (referred to v ih min of the scl signal) in order to bridge the undefined region of scls falling edge. 4 c b is the total capacitance of one bus line in pf. t r and t f measured between 0.3 v dd and 0.7 v dd .
ad5305/ad5315/ad5325 rev. g | page 6 of 24 scl s d a start condition t 9 t 4 t 3 t 10 t 5 t 11 t 2 t 6 t 1 t 8 t 4 t 7 repeated start condition stop condition 0 0930-002 figure 2. 2-wire serial interface timing diagram
ad5305/ad5315/ad5325 rev. g | page 7 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 4. parameter 1 rating v dd to gnd C0.3 v to +7 v scl, sda to gnd C0.3 v to v dd + 0.3 v a0 to gnd C0.3 v to v dd + 0.3 v reference input voltage to gnd C0.3 v to v dd + 0.3 v v out a to v out d to gnd C0.3 v to v dd + 0.3 v operating temperature range industrial (a, b version) ?40c to +105c storage temperature range ?65c to +150c junction temperature (t j max) 150c msop power dissipation (t j max ? t a )/ ja ja thermal impedance 206c/w jc thermal impedance 44c/w reflow soldering peak temperature 220c time at peak temperature 10 sec to 40 sec 1 transient currents of up to 100 ma do not cause scr latcth-up. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution esd (electrostatic discharge) sensitive device. electros tatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
ad5305/ad5315/ad5325 rev. g | page 8 of 24 pin configuration and fu nction descriptions 10 9 8 7 6 1 2 3 4 5 gnd sda scl refin a0 ad5305/ ad5315/ ad5325 top view (not to scale) v dd v out a v out b v out c v out d 00930-003 figure 3. pin configuration table 5. pin function descriptions pin no. mnemonic description 1 v dd power supply input. these parts can be operated from 2.5 v to 5.5 v and the supply should be decoupled to gnd. 2 v out a buffered analog output voltage from dac a. the output amplifier has rail-to-rail operation. 3 v out b buffered analog output voltage from dac b. the output amplifier has rail-to-rail operation. 4 v out c buffered analog output voltage from dac c. the output amplifier has rail-to-rail operation. 5 refin reference input pin for all four dacs. it has an input range from 0.25 v to v dd . 6 v out d buffered analog output voltage from dac d. the output amplifier has rail-to-rail operation. 7 gnd ground reference point for all circuitry on the part. 8 sda serial data line. this is used in conjunction with the scl line to clock data into or out of the 16-bit input shift register. it is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor. 9 scl serial clock line. this is used in conjunction with the sd a line to clock data into or out of the 16-bit input shift register. clock rates of up to 400 kb/s can be accommodated in the 2-wire interface. 10 a0 address input. sets the least sign ificant bit of the 7-bit slave address.
ad5305/ad5315/ad5325 rev. g | page 9 of 24 typical performance characteristics code inl error (lsb) 1.0 0.5 ?1.0 0 0 ?0.5 t a = 25c v dd = 5v 50 100 150 200 250 0 0930-006 figure 4. ad5305 typical inl plot inl error (lsb) 3 0 ?1 ?2 ?3 2 1 t a = 25c v dd = 5v code 0 200 400 600 800 1000 0 0930-007 figure 5. ad5315 typical inl plot inl error (lsb) 12 0 ?4 ?8 8 4 ?12 t a = 25c v dd = 5v code 0 1000 2000 3000 4000 00930-008 figure 6. ad5325 typical inl plot dnl error (lsb) 0.3 ?0.3 ?0.1 ?0.2 0.2 0.1 0 code 0 t a = 25c v dd = 5v 50 100 150 200 250 00930-009 figure 7. ad5305 typical dnl plot 0.6 0.4 ?0.2 ?0.6 0.2 0 ?0.4 code dnl error (lsb) 0 t a = 25c v dd = 5v 200 400 600 800 1000 00930-010 figure 8. ad5315 typical dnl plot 0.5 0 ?1.0 1.0 ?0.5 code dnl error (lsb) 0 1000 2000 3000 4000 t a = 25c v dd = 5v 00930-011 figure 9. ad5325 typical dnl plot
ad5305/ad5315/ad5325 rev. g | page 10 of 24 5 error (lsb) 0.50 0.25 ?0.50 0 ?0.25 v ref (v) 012 34 maxinl maxdnl min dnl min inl v dd = 5v t a = 25c 00930-012 figure 10. ad5305 inl and dnl error vs. v ref temperature (c) error (lsb) 0.5 0.2 ?0.5 0 ?0.2 ?0.4 ?0.3 ?0.1 0.1 0.3 0.4 ?40 0 40 80 120 max dnl min inl min dnl v dd = 5v v ref = 3v max inl 00930-013 figure 11. ad5305 inl and dnl error vs. temperature error (%) 1.0 0.5 ?1.0 0 ?0.5 temperature (c) ?40 0 40 80 120 v dd = 5v v ref = 2v 00930-014 offset error gain error figure 12. ad5305 offset error and gain error vs. temperature error (%) 0.2 ?0.6 0 ?0.4 ?0.5 ?0.3 ?0.2 ?0.1 0.1 t a = 25c v ref = 2v v dd (v) 0123456 00930-015 offset error gain error figure 13. offset error and gain error vs. v dd sink/source current (ma) 5 0 4 1 2 3 v out (v) 0123456 0 0930-016 5v source 3v sink 3v source 5v sink figure 14. v out source and sink current capability code 600 0 500 100 200 300 400 t a = 25c v dd = 5v v ref = 2v zero scale full scale i dd (a) 00930-017 figure 15. supply current vs. dac code
ad5305/ad5315/ad5325 rev. g | page 11 of 24 600 0 500 100 200 300 400 v dd (v) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 i dd (a) ?40c +105c +25c 00930-018 figure 16. supply current vs. supply voltage 0.5 0 0.4 0.1 0.2 0.3 v dd (v) 2.5 3.0 3.5 4.0 4.5 5.0 5.5 i dd (a) ?40c +105c +25c 00930-019 figure 17. power-down current vs. supply voltage 750 450 550 650 v logic (v) 012345 i dd (a) t a = 25c v dd = 5v v dd = 3v decreasing increasing 00930-020 figure 18. supply current vs. logic input voltage for sda and scl voltage increasing and decreasing ch1 ch2 scl ch1 1v, ch2 5v, time base = 1s/div t a = 25c v dd = 5v v ref = 5v v out a 00930-021 figure 19. half-scale settling (1/4 to 3/4 scale code change) ch1 2v, ch2 200mv, time base = 200s/div ch1 ch2 t a = 25c v dd = 5v v ref = 2v v out a v dd 0 0930-022 figure 20. power-on reset to 0 v ch1 500mv, ch2 5v, time base = 1s/div ch1 ch2 v out a t a = 25c v dd = 5v v ref = 2v scl 00930-023 figure 21. exiting po wer-down to midscale
ad5305/ad5315/ad5325 rev. g | page 12 of 24 frequency i dd (a) 300 350 400 450 500 550 600 v dd = 5v v dd = 3v 00930-024 figure 22. i dd histogram with v dd = 3 v and v dd = 5 v 1s/div 2.48 2.49 2.47 2.50 v out (v) 00930-025 figure 23. ad5325 major-code transition glitch energy frequency (hz) 10 ?40 10 ?20 ?30 0 ?10 (db) ?50 ?60 100 1k 10k 100k 1m 10m 00930-026 figure 24. multiplying bandwidth (small-signal frequency response) full scale error (v) 0.02 0.01 ?0.02 0 ?0.01 v dd = 5v t a = 25c v ref (v) 01 23456 0 0930-027 figure 25. full-scale error vs. v ref 50ns/div 1mv/di v 00930-028 figure 26. dac-to -dac crosstalk
ad5305/ad5315/ad5325 rev. g | page 13 of 24 terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsb, from a straight line passing through the endpoints of the dac transfer function. typical inl versus code plots can be seen in figure 4 , figure 5 , and figure 6 . differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. typical dnl vs. code plots can be seen in figure 7 , figure 8 , and figure 9 . offset error this is a measure of the offset error of the dac and the output amplifier. it is expressed as a percentage of the full-scale range. gain error this is a measure of the span error of the dac. it is the deviation in slope of the actual dac transfer characteristic from the ideal expressed as a percentage of the full-scale range. offset error drift this is a measure of the change in offset error with changes in temperature. it is expressed in (ppm of full-scale range)/c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/c. power supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in v out to a change in v dd for full-scale output of the dac. it is measured in db. v ref is held at 2 v and v dd is varied 10%. dc crosstalk this is the dc change in the output level of one dac at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of another dac. it is expressed in v. reference feedthrough this is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated. it is expressed in db. major-code transition glitch energy major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the dac register changes state. it is normally specified as the area of the glitch in nv-s and is measured when the digital code is changed by 1 lsb at the major carry transition (011 . . . 11 to 100 . . . 00, or 100 . . . 00 to 011 . . . 11). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital input pins of the device when the dac output is not being updated. it is specified in nv-s and is measured with a worst-case change on the digital input pins, for example, from all 0s to all 1s or vice versa. digital crosstalk this is the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is expressed in nv-s. dac-to-dac crosstalk this is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s and vice versa) with the ldac bit set low and monitoring the output of another dac. the energy of the glitch is expressed in nv-s. multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the frequency at which the output amplitude falls to 3 db below the input. total harmonic distortion (thd) this is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac and the thd is a measure of the harmonics present on the dac output. it is measured in db.
ad5305/ad5315/ad5325 rev. g | page 14 of 24 d e a d b a n d c o d e s amplifier footroom (1mv) negative offset error actual ideal dac code negative offset error output voltage gain error plus offset error 00930-004 figure 27. transfer functi on with negative offset dac code actual ideal output voltage positive offset gain error plus offset error 00930-005 figure 28. transfer function with positive offset
ad5305/ad5315/ad5325 rev. g | page 15 of 24 functional description the ad5305/ad5315/ad5325 are quad resistor-string dacs fabricated on a cmos process with resolutions of 8, 10, and 12 bits, respectively. each contains four output buffer amplifiers and is written to via a 2-wire serial interface. they operate from single supplies of 2.5 v to 5.5 v, and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 v/s. the four dacs share a single reference input pin. the devices have three programmable power-down modes, in which all dacs can be turned off completely with a high impedance output, or the outputs can be pulled low by on-chip resistors. digital-to-analog section the architecture of one dac channel consists of a resistor- string dac followed by an output buffer amplifier. the voltage at the refin pin provides the reference voltage for the dac. figure 29 shows a block diagram of the dac architecture. because the input coding to the dac is straight binary, the ideal output voltage is given by n ref out dv v 2 = where: d = decimal equivalent of the binary code, which is loaded to the dac register: 0 to 255 for ad5305 (8 bits) 0 to 1023 for ad5315 (10 bits) 0 to 4095 for ad5325 (12 bits) n = dac resolution refin input register dac register resistor string output buffer amplifier v out a 00930-029 figure 29. dac channel architecture resistor string the resistor string section is shown in figure 30 . it is simply a string of resistors, each of value r. the digital code loaded to the dac register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. r r r r r to output amplifier 00930-030 figure 30. resistor string dac reference inputs there is a single reference input pin for the four dacs. the reference input is unbuffered. the user can have a reference voltage as low as 0.25 v and as high as v dd because there is no restriction due to headroom and footroom of any reference amplifier. it is recommended to use a buffered reference in the external circuit (for example, ref192). the input impedance is typically 45 k. output amplifier the output buffer amplifier is capable of generating rail-to-rail voltages on its output, which gives an output range of 0 v to v dd when the reference is v dd . it is capable of driving a load of 2 k to gnd or v dd , in parallel with 500 pf to gnd or v dd . the source and sink capabilities of the output amplifier can be seen in the plot in figure 14 . the slew rate is 0.7 v/s with a half-scale settling time to 0.5 lsb (at eight bits) of 6 s. power-on reset the ad5305/ad5315/ad5325 are provided with a power-on reset function, so that they power up in a defined state. the power-on state is ? normal operation ? output voltage set to 0 v both input and dac registers are filled with zeros and remain so until a valid write sequence is made to the device. this is particularly useful in applications where it is important to know the state of the dac outputs while the device is powering up.
ad5305/ad5315/ad5325 rev. g | page 16 of 24 serial interface the ad5305/ad5315/ad5325 are controlled via an i 2 c compatible serial bus. the dacs are connected to this bus as slave devices (that is, no clock is generated by the ad5305/ ad5315/ad5325 dacs). this interface is smbus compatible at v dd < 3.6 v. the ad5305/ad5315/ad5325 have a 7-bit slave address. the 6 msb are 000110 and the lsb is determined by the state of the a0 pin. the facility to make hardwired changes to a0 allows the user to use up to two of these devices on one bus. the 2-wire serial bus protocol operates as follows: 1. the master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the sda line occurs while scl is high. the following byte is the address byte, which consists of the 7-bit slave address followed by an r/ w bit (this bit determines whether data is read from or written to the slave device). the slave whose address corresponds to the transmitted address responds by pulling sda low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its shift register. 2. data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). the transitions on the sda line must occur during the low period of scl and remain stable during the high period of scl. 3. when all data bits have been read or written, a stop condition is established. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition. in read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the sda line remains high). the master then brings the sda line low before the 10 th clock pulse and then high during the 10 th clock pulse to establish a stop condition. read/write sequence in the case of the ad5305/ad5315/ad5325, all write access sequences and most read sequences begin with the device address (with r/ w = 0) followed by the pointer byte. this pointer byte specifies the data format and determines which dac is being accessed in the subsequent read/write operation (see figure 31 ). in a write operation, the data follows immediately. in a read operation, the address is resent with r/ w = 1 and then the data is read back. however, it is also possible to perform a read operation by sending only the address with r/ w = 1. the previously loaded pointer settings are then used for the readback operation. see figure 32 for a graphical explanation of the interface. dacd x x lsb msb 00 dacc dacb daca 0 0930-031 figure 31. pointer byte pointer byte bits table 6 explains the individual bits that make up the pointer byte. table 6. individual bits of the pointer byte bit description x dont care bits. 0 reserved bits. must be set to 0. dacd [1] the following data bytes are for dac d. dacc [1] the following data bytes are for dac c. dacb [1] the following data bytes are for dac b. daca [1] the following data bytes are for dac a. input shift register the input shift register is 16 bits wide. data is loaded into the device as two data bytes on the serial data line, sda, under the control of the serial clock input, scl. the timing diagram for this operation is shown in figure 2 . the two data bytes consist of four control bits followed by 8, 10, or 12 bits of dac data, depending on the device type. the first two bits loaded are the pd1 and pd0 bits that control the mode of operation of the device. see the power-down modes section for a complete description. bit 13 is clr , bit 12 is ldac , and the remaining bits are left justified dac data bits, starting with the msb. see figure 32 . data bytes (write and readback) most significant data byte pd0 pd1 lsb pd0 clr ldac pd1 pd1 lsb msb 10-bit ad5315 lsb msb 12-bit ad5325 clr ldac msb 8-bit ad5305 clr ldac d7 d6 d5 d4 d9 d8 d7 d6 pd0 d11 d10 d9 d8 least significant data byte lsb lsb msb 10-bit ad5315 lsb msb 12-bit ad5325 msb 8-bit ad5305 d2 d3 d1 d0 0 0 0 0 d4 d5 d3 d2 d1 d0 0 0 d6 d7 d5 d4 d3 d2 d1 d0 00930-032 figure 32. data formats for write and readback
ad5305/ad5315/ad5325 rev. g | page 17 of 24 table 7. clr and ldac bit descriptions bit description clr [0] all dac registers and input registers are filled with 0s on completion of the write sequence. [1] normal operation. ldac [0] all four dac registers and, therefore, all dac outputs, are simultaneously updated on completion of the write sequence. [1] only addressed input register is updated. there is no change in the contents of the dac registers. default readback condition all pointer byte bits power up to 0. therefore, if the user initiates a readback without writing to the pointer byte first, no single dac channel has been specified. in this case, the default readback bits are all 0, except for the clr bit, which is a 1. multiple-dac write sequence because there are individual bits in the pointer byte for each dac, it is possible to simultaneously write the same data and control bits to 2, 3, or 4 dacs by setting the relevant bits to 1. multiple-dac readback sequence if the user attempts to read back data from more than one dac at a time, the part reads back the default, power-on reset conditions, that is, all 0s except for clr , which is 1. write operation when writing to the ad5305/ad5315/ad5325 dacs, the user must begin with an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. this address byte is followed by the pointer byte, which is also acknowledged by the dac. two bytes of data are then written to the dac, as shown in figure 33 . a stop condition follows. read operation when reading data back from the ad5305/ad5315/ad5325 dacs, the user begins with an address byte (r/ w = 0), after which the dac acknowledges that it is prepared to receive data by pulling sda low. this address byte is usually followed by the pointer byte, which is also acknowledged by the dac. following this, there is a repeated start condition by the master and the address is resent with r/ w = 1. this is acknowledged by the dac indicating that it is prepared to transmit data. two bytes of data are then read from the dac, as shown in figure 34 . a stop condition follows. however, if the master sends an ack and continues clocking scl (no stop is sent), the dac retransmits the same two bytes of data on sda. this allows continuous readback of data from the selected dac register. alternatively, the user can send a start followed by the address with r/ w = 1. in this case, the previously loaded pointer settings are used and readback of data can commence immediately. address byte scl sd a scl sd a pointer byte least significant data byte ack by ad53x5 most significant data byte msb lsb msb lsb stop cond by master ack by ad53x5 ack by ad53x5 start cond by master ack by ad53x5 msb lsb 0 0 0 1 1 0 a0 r/w x x 00930-033 figure 33. write sequence
ad5305/ad5315/ad5325 rev. g | page 18 of 24 scl s d a scl s d a note: data bytes are the same as those in the write sequence except that don?t cares are read back as 0s. scl s d a address byte pointer byte ack by ad53x5 start cond by master ack by ad53x5 msb lsb 0 0 0 1 1 0 a0 r/w x x data byte ack by ad53x5 address byte msb lsb ack by master 0 0 0 1 1 0 a0 r/w msb lsb no ack by master repeated start cond by master stop cond by master least significant data byte 00930-034 figure 34. readback sequence double-buffered interface the ad5305/ad5315/ad5325 dacs have double-buffered interfaces consisting of two banks of registersinput registers and dac registers. the input register is directly connected to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. the dac register contains the digital code used by the resistor string. access to the dac register is controlled by the ldac bit. when the ldac bit is set high, the dac register is latched and, therefore, the input register can change state without affecting the contents of the dac register. however, when the ldac bit is set low, the dac register becomes transparent and the contents of the input register are transferred to it. this is useful if the user requires simultaneous updating of all dac outputs. the user can write to three of the input registers individually and then, by setting the ldac bit low when writing to the remaining dac input register, all outputs update simultaneously. these parts contain an extra feature whereby the dac register is not updated unless its input register has been updated since the last time that ldac was brought low. normally, when ldac is brought low, the dac registers are filled with the contents of the input registers. in the case of the ad5305/ad5315/ ad5325, the part updates the dac register only if the input register has been changed since the last time the dac register was updated, thereby removing unnecessary digital crosstalk. power-down modes the ad5305/ad5315/ad5325 have very low power consumption, dissipating typically 1.5 mw with a 3 v supply and 3 mw with a 5 v supply. power consumption can be further reduced when the dacs are not in use by putting them into one of three power-down modes, which are selected by bit 15 and bit 14 (pd1 and pd0) of the data byte. table 8 shows how the state of the bits corresponds to the mode of operation of the dac. table 8. pd1/pd0 operating modes pd1 pd0 operating mode 0 0 normal operation 0 1 power-down (1 k load to gnd) 1 0 power-down (100 k load to gnd) 1 1 power-down (three-state output)
ad5305/ad5315/ad5325 rev. g | page 19 of 24 when both bits are set to 0, the dac works normally with its normal power consumption of 600 a at 5 v. however, for the three power-down modes, the supply current falls to 200 na at 5 v (80 na at 3 v). not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. this has an advantageous because the output impedance of the part is known while the part is in power-down mode and provides a defined input condition for whatever is connected to the output of the dac amplifier. there are three different options. the output is connected internally to gnd through a 1 k resistor, a 100 k resistor, or it is left open-circuited (three-state). resistor tolerance = 20%. the output stage is illustrated in figure 35 . amplifier resistor string dac power-down circuitry v out resistor network 00930-035 figure 35. output stage during power-down the bias generator, the output amplifiers, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. however, the contents of the dac registers are unchanged when in power-down. the time to exit power-down is typically 2.5 s for v dd = 5 v and 5 s when v dd = 3 v. this is the time from the rising edge of the eighth scl pulse to when the output voltage deviates from its power- down voltage. see figure 21 for a plot.
ad5305/ad5315/ad5325 rev. g | page 20 of 24 applications typical application circuit the ad5305/ad5315/ad5325 can be used with a wide range of reference voltages where the devices offer full, one-quadrant multiplying capability over a reference range of 0 v to v dd . more typically, these devices are used with a fixed, precision reference voltage. suitable references for 5 v operation are the ad780 and ref192 (2.5 v references). for 2.5 v operation, a suitable external reference is the ad589 , a 1.23 v band gap reference. figure 36 shows a typical setup for the ad5305/ ad5315/ad5325 when using an external reference. note that a0 can be high or low. gnd sda 0.1f refin a0 10f 1f scl v dd = 2.5v to 5.5 v v in ext ref v out ad780/ref192 with v dd = 5v or ad589 with v dd = 2.5v ad5305/ ad5315/ ad5325 v out d v out c v out b v out a serial interface 00930-036 figure 36. ad5305/ad5315/ad5325 using external reference if an output range of 0 v to v dd is required, the simplest solution is to connect the reference input to v dd . as this supply may not be very accurate and may be noisy, the ad5305/ad5315/ad5325 can be powered from the reference voltage; for example, using a 5 v reference such as the ref195. the ref195 outputs a steady supply voltage for the ad5305/ ad5315/ad5325. the typical current required from the ref195 is 600 a supply current and approximately 112 a into the reference input. this is with no load on the dac outputs. when the dac outputs are loaded, the ref195 also needs to supply the current to the loads. the total current required (with a 10 k load on each output) is 712 a + 4(5 v/10 k) = 2.70 ma the load regulation of the ref195 is typically 2 ppm/ma, which results in an error of 5.4 ppm (27 v) for the 2.7 ma current drawn from it. this corresponds to a 0.0014 lsb error at eight bits and 0.022 lsb error at 12 bits. bipolar operation the ad5305/ad5315/ad5325 have been designed for single supply operation, but a bipolar output range is also possible using the circuit in figure 37 . this circuit gives an output voltage range of 5 v. rail-to-rail operation at the amplifier output is achievable using an ad820 or an op295 as the output amplifier. +5v ?5v 10f 6v to 12v ad5305 0.1f r1 = 10k ? 5v r2 = 10k ? refin a0 g n d ad1585 1f +5v v dd 2-wire serial interface v out d v out c v out b v out a v in v out 00930-037 gnd scl sda ad820/ op295 figure 37. bipolar operation with the ad5305 the output voltage for any input code can be calculated as follows: u uu 1/2 1 212/ rrrefin r rrdrefin v n out where: d is the decimal equivalent of the code loaded to the dac. n is the dac resolution. refin is the reference voltage input. with refin = 5 v, r1 = r2 = 10 k, v out (10 d /2 n ) ? 5 v multiple devices on one bus figure 38 shows two ad5305 devices on the same serial bus. each has a different slave address because the state of the a0 pin is different. this allows each of eight dacs to be written to or read from independently. scl sda ad5305 a0 ad5305 scl sda a0 micro- controller pull-up resistors v dd 00930-038 figure 38. multiple ad5305 devices on one bus
ad5305/ad5315/ad5325 rev. g | page 21 of 24 ad5305/ad5315/ad5325 as a digitally programmable window detector a digitally programmable upper/lower limit detector using two of the dacs in the ad5305/ad5315/ad5325 is shown in figure 39 . the upper and lower limits for the test are loaded to dac a and dac b, which, in turn, set the limits on the cmp04. if the signal at the v in input is not within the programmed window, an led indicates the fail condition. similarly, dac c and dac d can be used for window detection on a second v in signal. 5 v gnd refin 1/6 74hc05 fail pass 1k ? scl sda scl din 1k ? 1 additional pins omitted for clarity. 0.1f 10f v ref 1/2 ad5305/ ad5315/ ad5325 1 v out a v out b v dd v in 1/2 cmp04 pass/fail 00930-039 figure 39. window detection coarse and fine adjustment using the ad5305/ad5315/ad5325 two of the dacs in the ad5305/ad5315/ad5325 can be paired together to form a coarse and fine adjustment function, as shown in figure 40 . dac a is used to provide the coarse adjustment while dac b provides the fine adjustment. varying the ratio of r1 and r2 changes the relative effect of the coarse and fine adjustments. with the resistor values and external reference shown in figure 40 , the output amplifier has unity gain for the dac a output. as a result, the output range is 0 v to 2.5 v ? 1 lsb. for dac b, the amplifier has a gain of 7.6 10 ?3 , giving dac b a range equal to 19 mv. similarly, dac c and dac d can be paired together for coarse and fine adjustment. the circuit is shown with a 2.5 v reference, but reference voltages up to v dd can be used. the op amps indicated allows a rail-to-rail output swing. 1f refin gnd 0.1f 10f gnd 5v v out 1 additional pins omitted for clarity. r3 51.2k ? r4 390 ? r1 390 ? r2 51.2k ? ad820/ op295 v dd = 5v v dd v out a v out b 1/2 ad5305/ ad5315/ ad5325 1 ad780/ref192 with v dd = 5v v out v in ext ref 00930-040 figure 40. coarse/fine adjustment power supply decoupling in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the ad5305/ad5315/ad5325 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. if the ad5305/ad5315/ad5325 is in a syst em where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. the ad5305/ ad5315/ad5325 should have ample supply bypassing of 10 f in parallel with 0.1 f on the supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective series resistance (esr) and effective series inductance (esi), such as the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. the power supply lines of the ad5305/ad5315/ad5325 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. a ground line routed between the sda and scl lines helps reduce crosstalk between them (not required on a multilayer board as there is a separate ground plane, but separating the lines does help). avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feedthrough through the board. a microstrip technique is by far the best, but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side.
ad5305/ad5315/ad5325 rev. g | page 22 of 24 table 9 . overview of all ad53xx serial devices part no. resolution no. of dacs dnl interface settling time (s) package pins singles ad5300 8 1 0.25 spi? 4 sot-23, msop 6, 8 ad5310 10 1 0.5 spi 6 sot-23, msop 6, 8 ad5320 12 1 1.0 spi 8 sot-23, msop 6, 8 ad5301 8 1 0.25 2-wire 6 sot-23, msop 6, 8 ad5311 10 1 0.5 2-wire 7 sot-23, msop 6, 8 ad5321 12 1 1.0 2-wire 8 sot-23, msop 6, 8 duals ad5302 8 2 0.25 spi 6 msop 8 ad5312 10 2 0.5 spi 7 msop 8 ad5322 12 2 1.0 spi 8 msop 8 ad5303 8 2 0.25 spi 6 tssop 16 ad5313 10 2 0.5 spi 7 tssop 16 ad5323 12 2 1.0 spi 8 tssop 16 quads ad5304 8 4 0.25 spi 6 msop 10 ad5314 10 4 0.5 spi 7 msop 10 ad5324 12 4 1.0 spi 8 msop 10 ad5305 8 4 0.25 2-wire 6 msop 10 ad5315 10 4 0.5 2-wire 7 msop 10 ad5325 12 4 1.0 2-wire 8 msop 10 ad5306 8 4 0.25 2-wire 6 tssop 16 ad5316 10 4 0.5 2-wire 7 tssop 16 ad5326 12 4 1.0 2-wire 8 tssop 16 ad5307 8 4 0.25 spi 6 tssop 16 ad5317 10 4 0.5 spi 7 tssop 16 ad5327 12 4 1.0 spi 8 tssop 16 octals ad5308 8 8 0.25 spi 6 tssop 16 ad5318 10 8 0.5 spi 7 tssop 16 ad5328 12 8 1.0 spi 8 tssop 16 table 10 . overview of ad53xx parallel devices part no. resolution dnl v ref pins settling time (s) additional pin functions package pins singles buf gain hben clr ad5330 8 0.25 1 6 ? ? ? tssop 20 ad5331 10 0.5 1 7 ? ? tssop 20 ad5340 12 1.0 1 8 ? ? ? tssop 24 ad5341 12 1.0 1 8 ? ? ? ? tssop 20 duals ad5332 8 0.25 2 6 ? tssop 20 ad5333 10 0.5 2 7 ? ? ? tssop 24 ad5342 12 1.0 2 8 ? ? ? tssop 28 ad5343 12 1.0 1 8 ? ? tssop 20 quads ad5334 8 0.25 2 6 ? ? tssop 24 ad5335 10 0.5 2 7 ? ? tssop 24 ad5336 10 0.5 4 7 ? ? tssop 28 ad5344 12 1.0 4 8 tssop 28
ad5305/ad5315/ad5325 rev. g | page 23 of 24 outline dimensions compliant to jedec standards mo-187-ba 0.23 0.08 0.80 0.60 0.40 8 0 0.15 0.05 0.33 0.17 0.95 0.85 0.75 seating plane 1.10 max 10 6 5 1 0.50 bsc pin 1 coplanarity 0.10 3.10 3.00 2.90 3.10 3.00 2.90 5.15 4.90 4.65 figure 41. 10-lead mini small outline package [msop] (rm-10) dimensions shown in millimeters ordering guide model temperature range package desc ription package option branding ad5305arm ?40c to +105c 10-lead msop rm-10 dea ad5305arm-reel7 ?40c to +105c 10-lead msop rm-10 dea ad5305armz 1 ?40c to +105c 10-lead msop rm-10 d99 ad5305armz-reel7 1 ?40c to +105c 10-lead msop rm-10 d99 ad5305brm ?40c to +105c 10-lead msop rm-10 deb ad5305brm-reel ?40c to +105c 10-lead msop rm-10 deb ad5305brm-reel7 ?40c to +105c 10-lead msop rm-10 deb ad5305brmz 1 ?40c to +105c 10-lead msop rm-10 deb # ad5305brmz-reel7 1 ?40c to +105c 10-lead msop rm-10 deb # ad5315arm ?40c to +105c 10-lead msop rm-10 dfa ad5315arm-reel7 ?40c to +105c 10-lead msop rm-10 dfa ad5315armz 1 ?40c to +105c 10-lead msop rm-10 d8e ad5315brm ?40c to +105c 10-lead msop rm-10 dfb ad5315brm-reel ?40c to +105c 10-lead msop rm-10 dfb ad5315brm-reel7 ?40c to +105c 10-lead msop rm-10 dfb ad5315brmz 1 ?40c to +105c 10-lead msop rm-10 d6n ad5315brmz-reel 1 ?40c to +105c 10-lead msop rm-10 d6n ad5315brmz-reel7 1 ?40c to +105c 10-lead msop rm-10 d6n ad5325arm ?40c to +105c 10-lead msop rm-10 dga ad5325arm-reel7 ?40c to +105c 10-lead msop rm-10 dga ad5325armz 1 ?40c to +105c 10-lead msop rm-10 d8g ad5325brm ?40c to +105c 10-lead msop rm-10 dgb ad5325brm-reel ?40c to +105c 10-lead msop rm-10 dgb ad5325brm-reel7 ?40c to +105c 10-lead msop rm-10 dgb ad5325brmz 1 ?40c to +105c 10-lead msop rm-10 d8h ad5325brmz-reel 1 ?40c to +105c 10-lead msop rm-10 d8h AD5325BRMZ-REEL7 1 ?40c to +105c 10-lead msop rm-10 d8h 1 z = pb-free part; # denotes lead-free product may be top or bottom marked.
ad5305/ad5315/ad5325 rev. g | page 24 of 24 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associated companies conveys a license for the purchaser under the phi lips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. c00930-0-5/06(g)

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